Architecture of a Neuroprocessor Chip for Pulse-Coded Neural Networks
نویسندگان
چکیده
We present the architecture of a processor chip to be fabricated in digital VLSI-technology which computes the function of a configurable spiking neuron model. The chip is a submodule of the MASPINN-System (Memory Optimized Accelerator for Spiking Neural Networks). The MASPINN-System is designed as a PCI-accelerator-board for real-time simulation of very complex networks of spiking neurons in the order of 106 neurons. Such a performance is desirable for image processing or simulations of brain regions. Within the MASPINN-System, the neuroprocessor chip processes the essential function of a spiking neuron. It models different types of postsynaptic potentials, combines these potentials to a membrane potential and based upon a dynamic threshold, it decides on spike emission. To achieve real-time simulation of very complex spiking neural networks, the architecture emphasizes parallelization in processing and reduction of bandwidth requirements.
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